There is often a need to phase-lock two or more RF signal sources so that there is no frequency drift between the signal sources. This discussion will be limited to the case where the RF signal sources are of the ubiquitous integer phase-lock loop (PLL) type. A necessary condition is that the two sources have references that are traceable to the same physical oscillator, such as a 10 MHz crystal oscillator. Phase-locking two integer PLLs can be as simple as providing the same reference to both PLLs. This will ensure that the two PLLs, when tuned to the same frequency, will have zero frequency error and that the static phase error between the two signals will not change (i.e., phase-locked).

A more complicated requirement is to have the two integer PLLs always have the same phase relationship when tuned to the same frequency. This entails a deeper understanding of the actual design of the two PLLs.

NuWaves’ Multi-Octave RF Upconverter (MORF) provides an external reference input that can enable the phase-locking with another source.

Two PLLs using the same reference will inherently exhibit different, though static, phase relationships depending on how the two PLLs become phase-locked to a common reference. The number of different phase relationships between the two PLLs depends on the reference divider value (R) within each PLL. If the reference is divided by 10 before arriving at the PLL phase detector, for instance, then there will be 10 distinct phase states for any tuned output frequency. That is, the total number of possible phase states is equal to R, the reference divider value.

A straightforward solution to guaranteeing that two integer PLLs not only are phase-locked but also have a repeatable phase relationship is to choose R=1 for the reference division of each PLL, constraining each PLL to only one possible phase state. A reference value of 1 is effectively the same as having no division. This awareness suggests that any division of the reference should be done by a common circuit (i.e., prior entering an individual PLL), with the divided-down result sourcing both PLLs. Otherwise the phase relationship between two phase-locked integer PLLs is not repeatable.

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